Former Microsoft Engineer Builds RAM Card for PDP-11 Computer

    Former Microsoft engineer Dave Plummer has developed a new RAM card for the PDP-11 computer, which was released in 1970. He began the project after discovering that 1 MB of memory compatible with the old system was prohibitively expensive. Plummer, who had little experience with complex electronics projects, used ChatGPT and the online schematic design tool EasyEDA. Later PDP-11 models supported up to 4 MB of memory.    Plummer designed the RAM module as a separate Q-Bus card. He then tested it on the same connector board as the M8190 processor card. Memory operation is controlled by a programmable FPGA chip called the Lattice MachXO2 2000HC. The board has four 1 MB memory chips from ISSI. It also includes a U2S input-output chip, DIP switches, communication ports and capacitors.    The project's first test was unsuccessful. Plummer encountered several problems because he had never written software for an FPGA chip before. In addition, the upper 256 KB region of the M8190 card's 22-bit data line is reserved for input-output ports and ROM. The PDP-11 reads not an individual byte from memory, but a complete word consisting of 2 bytes. The least significant bit of the address determines which byte is selected from that word.    Because the first controller did not account for this rule, the memory returned only every second word. As a result, the 4 MB of memory effectively operated as 2 MB. No subsequent update has been shared, but the problem can be resolved by modifying the FPGA code. A Raspberry Pi has also been proposed as a software-based solution. Plummer said the previous week that he had already tested a similar system using QBone and Beaglebone Black.